Soundaware boasts a history spanning over a decade in decoder production. Even with delta-sigma chips, it has created commemorative models like A300, as well as previous offerings such as MR2, MR1V2, and A280. The primary reason for not introducing an independent decoder is the unavailability of the core SPDIF reception technology within the company's scope.
As commonly understood, SPDIF reception chips like dir9001, WM8805, CS8416, AK41XX, and others have existed for decades. These chips possess the shared advantage of being user-friendly and capable of producing pleasing sound, much like Soundaware's earlier products, which have gained widespread use. When developing a product valued at several or tens of thousands of yuan, it's deemed acceptable to employ a similar chip. However, in reality, these chips exhibit nearly 200ps of receiving jitter. By optimizing the backend power supply, digital-to-analog conversion (DA), and low-pass filtering (LPF), this level of performance can be achieved, yielding satisfactory results.
However, have you ever noticed that genuinely high-end decoders avoid using this type of chip? Even if they utilize such chips, they often incorporate another self-developed or clock processing-oriented chip in the backend, before the signal enters the digital-to-analog (DA) conversion process.
Our observation indicates that top-tier decoders don't commonly rely on standardized solutions for SPDIF reception and subsequent IIS conversion. Instead, they tend to opt for self-developed methods, DSP or CPLD utilization, or a preliminary public version solution, followed by additional chip-level processing. This strategy elevates their performance to the next level. Over the span of more than a decade, Soundaware has dedicated its efforts to refining digital IIS processing and achieving low-jitter SPDIF transmission. Furthermore, it's worth noting that the default upper limit for the SPDIF protocol is 192kHz, and DSD transmission is limited to DOP due to the absence of specific regulations. This inherent limitation has led to the gradual weakening of the SPDIF protocol's capabilities.
Consequently, after 2014, diminished attention and investment were directed toward SPDIF. Soundaware, having already become highly proficient in implementing the SPDIF protocol, had independently developed and launched a high-definition SPDIF solution in 2011, based on FPGA technology. While reception was indeed feasible, a lack of comprehensive mass production development and extensive testing resulted from the aforementioned constraints. It wasn't until the inception of the dream decoding scheme that a renewed investment and research effort was undertaken, eventually leading to a breakthrough.
The receiving chip in the final product now undergoes conversion from SPDIF to IIS. Due to constraints imposed by CMOS technology and PLL, the typical jitter level tends to exceed 50ps, with actual PCB implementations generally ranging from approximately 100 to 200ps. The Jinling DSP's decoding design, however, manages to achieve clock jitter levels as low as 5ps for key components. By bypassing the high-jitter CMOS and PLL and integrating an external ultra-low jitter clock along with a high-performance power supply, the overall clock jitter can be reduced to a remarkable 5ps level. This substantial improvement leads to a dramatic enhancement in IIS quality. This is the reason why, as showcased in the new audio magazine, even when connecting the coaxial output based on CDP to the coaxial input of DAM1—despite undergoing two conversions—the coaxial transmission maintains a level of comparison with the original IIS within the unit without any conversion. Even upscale integrated CD players priced over $10,000 find it hard to match this performance leap. This improvement represents a significant leap that is unlikely to be surpassed.
Many audio enthusiasts have encountered numerous new decoders that offer satisfactory USB sound. However, upon using coaxial, optical, or AES connections, the sound quality tends to significantly degrade. Even among some flagship decoders we've encountered, the sound quality of the coaxial output is inferior to USB by one or two levels.
Breakthroughs in core technology are never mere accidents. In the realm of HIFI, learning opportunities are scarce, and hi-end manufacturers don't share proprietary core technology. Instead, manufacturers need to make gradual progress, navigating through numerous trials and setbacks. The SPDIF receiver in DAM1 not only boasts significantly enhanced conversion capabilities compared to default chip solutions but also supports higher sampling rates, currently reaching up to 384kHz and DSD128.
Simultaneously, through diligent efforts by the company's firmware research and development department, switching noise has been minimized to industry-leading levels. The introduction of internal automatic pop detection, automatic mute functions, and an array of pop and mute processing has elevated the functionality, user experience, and performance of SPDIF reception to unprecedented heights.